// 78;Simplorer1.sml
//*************************************************************************************************
//                                           SML Netlist File                                     
//                                   created by Ansys Twin Builder 2025.2                            
//                                                                                                
//*************************************************************************************************

INTERN EQU 
{
	I1:=0;
} DST: SIM(Type:=SFML, Sequ:=DSN_PARAM);
// Global Ports


// begin toplevel circuit

MODEL MaxwellECEData3 ECE1 A0:= net_2, X0:= net_1, B0:= net_3, Y0:= net_1, C0:= net_4, Z0:= net_1, TRB1:= net_6, TRB2:= GND ( ra0:=0.001, la0:=1e-06, IniIa0:=0, IniIb0:=0, IniIc0:=0) SRC: DB(Lib:=) ;
INTERN ISINE I1 N1:= GND , N2:= net_2 (FREQ:= 50, TPERIO:=Tend + 1, AMPL:=I1, PHASE:=0, PERIO:=0, OFF:=0, TDELAY:=0, AC_PHASE := 0, AC_MAG := 0.001);
INTERN ISINE I2 N1:= GND , N2:= net_3 (FREQ:= 50, TPERIO:=Tend + 1, AMPL:=I1, PHASE:=-120, PERIO:=0, OFF:=0, TDELAY:=0, AC_PHASE := 0, AC_MAG := 0.001);
INTERN ISINE I3 N1:= GND , N2:= net_4 (FREQ:= 50, TPERIO:=Tend + 1, AMPL:=I1, PHASE:=120, PERIO:=0, OFF:=0, TDELAY:=0, AC_PHASE := 0, AC_MAG := 0.001);
INTERN VM VM1 N1:= net_2 , N2:= net_1 ( ) ;
INTERN VM VM2 N1:= net_3 , N2:= net_1 ( ) ;
INTERN VM VM3 N1:= net_4 , N2:= net_1 ( ) ;
UMODEL V_TRB V_TRB1 TRB1:= net_6, TRB2:= GND ( AC_PHASE := 0, AC_MAG := 0.001, S0:= 0.036, VALUE:= 3.6) SRC: DB(Lib:= "Simplorer Elements\Basic Elements\Basic Elements") ;
// end toplevel circuit

SIMCTL TR
{
SIMCFG SIMPLORER_TR TR ( Tend := 0.02, Hmin := 1e-05, Hmax := 1e-05 );
}
OUTCTL OutCtl1
{
RESULT SDB SDB_0(I1.I);
RESULT SDB SDB_1(I1.V);
RESULT SDB SDB_2(I2.I);
RESULT SDB SDB_3(I2.V);
RESULT SDB SDB_4(I3.I);
RESULT SDB SDB_5(I3.V);
RESULT SDB SDB_6(VM1.V);
RESULT SDB SDB_7(VM2.V);
RESULT SDB SDB_8(VM3.V);
RESULT SDB SDB_9(V_TRB1.F);
RESULT SDB SDB_10(V_TRB1.V);
RESULT VIEW VANALOG_0(I1.I);
RESULT VIEW VANALOG_1(I1.V);
RESULT VIEW VANALOG_2(I2.I);
RESULT VIEW VANALOG_3(I2.V);
RESULT VIEW VANALOG_4(I3.I);
RESULT VIEW VANALOG_5(I3.V);
RESULT VIEW VANALOG_6(VM1.V);
RESULT VIEW VANALOG_7(VM2.V);
RESULT VIEW VANALOG_8(VM3.V);
RESULT VIEW VANALOG_9(V_TRB1.F);
RESULT VIEW VANALOG_10(V_TRB1.V);
OUTCFG VIEWTOOL VT1 ( Xmin := 0, Xmax := Tend);
OUTCFG SimplorerDB DB1 ( Xmin := 0, Xmax := Tend);
}